Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as medical, automobile, and other applications. High dynamic range (HDR) image sensors have been required by many of those applications. Human eyes normally possess a dynamic range of up to about 100 dB. For automobile applications, an image sensor of more than 100 dB dynamic range to deal with different driving conditions, such as driving through a dark tunnel into bright sunlight, is often required.
HDR image sensors do not always perform HDR functions properly. Common drawbacks include image degradation due to fixed pattern noise (FPN), large random noise, reduced resolution associated with charge blooming, motion artifacts, fixed sensitivity, and lower fill factor when multiple photodiodes are used, where fill factor is a ratio of a pixel's light sensitivity area to its total area.
When image sensors are used, photo-generated electrons in each of the plurality of pixel cells are transferred from the photodiode (PD) to the floating diffusion (FD) for subsequent readout. The transfer (TX) transistor coupled between the PD and the FD is switched on and off under the control of a voltage pulse asserted to the TX gate terminal to enable this charge transfer. Due to an always-presented coupling capacitance between the TX gate terminal and the FD, the pulse signal asserted on the TX gate is always largely coupled to the FD. This is called TX feed-through. It ripples through a source follower (SF) transistor and a row select (RS) transistor to an output line, also called a bitline, of the pixel cell. Such a propagation of a large unwanted pulse is unavoidable and causes annoying FPN even for dark signals (which are signals caused by non-photo-generated, intrinsic electrons inside the pixel). For any given bitline, since it connects to all the pixels in the column, it possesses a significant amount of capacitive and resistive (RC) load. Therefore, any state changes on the bitline are unavoidably slow due to this RC delay. That is, once a status changes happen on the bitline, it takes a long time to settle to the newly updated step level. This is governed by the so-called RC time constant. For any given input step Vin, its settling time is governed by
            t      settle        =                  τ        ·        ln            ⁢                          ⁢                        V                      i            ⁢                                                  ⁢            n                                    V                      0.5            ⁢                                                  ⁢            LSB                                ,where time constant τ=RC, and V0.5LSB is half the value of a single bit equivalent voltage.
One of the typical solutions to resolve this is to clamp the bitline voltage to limit its swing by using a clamp voltage generator. It helps suppressing the high-light-banding represented by voltages near its lower end. The goal is achieved by not allowing the bitline to drop below the clamped voltage limit. As a result, it reduces FPN under the high lighting conditions. However, this solution causes a large current variation to the power supply in react to each step voltage changes which in turn induces other unwanted performance issues on the sensor.
Another solution is to disconnect the pixel cell from its output line (bitline) during the charge transfer, also with the help of an added clamp voltage generator. The clamp voltage generator does not allow the bitline voltage to drop below a certain voltage level. Therefore, when the charge transfer takes place, the voltage change on bit lines can be reduced and settling time can be shortened. In addition, the total power supply (AVDD) current is maintained near constant by the clamp voltage generator to avoid large variations on the power supply. With this solution, after the RS transistor is switched back on again to reconnect the pixel output to the bitline, under complete dark condition which is correlated to the highest voltage, the bitline is charged by a pull-up-current through the SF transistor instead of being sunk by a pull-down-current of a relatively weak current source generator. Settling time is also reduced because the SF current is not limited by the current source generator. A faster pull up is always reached. That means, a faster settling on low lighting condition is clearly favored for this solution. Nevertheless, performance on strong lighting condition is still a problem, since higher contrasts in light intensities involve larger voltages drops on bitline which directly leads to a longer settling time.
Some solutions may offer decent result. However, they may involve fairly complex circuit such as amplifiers and controllers which occupy a lot of additional silicon area for each column readout circuit, and consumes more power to execute.
What's more, as size of pixel gets smaller and with higher conversion gains utilized, the FD capacitance may get so small that the TX feed-through may easily go beyond the range of the analog-to-digital converter (ADC) input voltage.
Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.